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Q. No.The output \(Y \) of the given logic implementation is similar to the output of which gate?
1.
OR
2.
NOR
3.
AND
4.
NAND
Subtopic: Logic gates |
Level 3: 35%-60%
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A full wave rectifier circuit with diodes \((D_1)\) and \((D_2)\) is shown in the figure. If input supply voltage \(V_{\text{in}}=220\sin(100\pi t)\) volt, then at \(t=15~\text{ms}\text{:}\)
| 1. | \(D_1\) and \(D_2\) both are forward biased |
| 2. | \(D_1\) and \(D_2\) both are reverse biased |
| 3. | Neither \(D_1\) nor \(D_2\) conducts at any time |
| 4. | \(D_1\) is reverse biased, \(D_2\) is forward biased |
Subtopic: Rectifier |
Level 3: 35%-60%
NEET - 2025
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The current \(I\) in the circuit shown below is:
(All diodes are ideal and identical.)
1. \(\dfrac{5}{3}~\text{A}\)
2. \(\dfrac{15}{2} ~\text{A}\)
3. \(\dfrac{1}{3} ~\text{A}\)
4. \(\dfrac{5}{9} ~\text{A}\)
(All diodes are ideal and identical.)
1. \(\dfrac{5}{3}~\text{A}\)
2. \(\dfrac{15}{2} ~\text{A}\)
3. \(\dfrac{1}{3} ~\text{A}\)
4. \(\dfrac{5}{9} ~\text{A}\)
Subtopic: PN junction |
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Level 2: 60%+
NEET - 2026
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In the circuit shown below, the voltage appearing across the diode \(D\) will be of the form:
| 1. |  |
| 2. |  |
| 3. |  |
| 4. |  |
Subtopic: PN junction |
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Level 2: 60%+
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Two statements are given below:
Choose the correct answer from the options given below:
| \((\mathrm{A})\) | When the forward bias voltage across a \(\mathrm{p\text{-}n}\) junction diode increases above a certain threshold voltage, the diode current increases significantly. |
| \((\mathrm{B})\) | This current is called reverse saturation current. |
| 1. | Both Statements \((\mathrm{A})\) and \((\mathrm{B})\) are False. |
| 2. | Statement \((\mathrm{A})\) is True, but Statement \((\mathrm{B})\) is False. |
| 3. | Both Statements \((\mathrm{A})\) and \((\mathrm{B})\) are True. |
| 4. | Statement \((\mathrm{A})\) is False, but Statement \((\mathrm{B})\) is True. |
Subtopic: PN junction |
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An ideal Zener diode with a breakdown voltage of \(-3~\text{V}\) is reverse-biased with a negative input voltage \(V_i=-5~\text{V}.\) The magnitude of the voltage difference between points \(B\) and \(A\) is:
1. \(0\) V
2. \(3\) V
3. \(2\) V
4. \(1\) V
1. \(0\) V
2. \(3\) V
3. \(2\) V
4. \(1\) V
Subtopic: Applications of PN junction |
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Level 3: 35%-60%
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Three identical \(\mathrm{p\text-n}\) junction diodes \(D_1\), \(D_2\) and \(D_3\) are connected across a battery as shown in the figure. If the width of the depletion regions of \(D_1\), \(D_2\) and \(D_3\) are \(W_1\), \(W_2\) and \(W_3\), respectively, then the correct option is:
1. \(W_2 > W_1 = W_3\)
2. \(W_1 > W_2 > W_3\)
3. \(W_3 = W_1 > W_2\)
4. \(W_3 > W_2 > W_1\)
1. \(W_2 > W_1 = W_3\)
2. \(W_1 > W_2 > W_3\)
3. \(W_3 = W_1 > W_2\)
4. \(W_3 > W_2 > W_1\)
Subtopic: PN junction |
Level 3: 35%-60%
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The output \(Y\) for the inputs \(A\) and \(B\) of the given logic circuit is:
| 1. | \(A\cdot B\) | 2. | \(\overline{A}\cdot\overline{B}\) |
| 3. | \(A+B\) | 4. | \(\overline{A}+\overline{B}\) |
Subtopic: Logic gates |
70%
Level 2: 60%+
NEET - 2024
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When the output of an OR gate is applied as input to a NOT gate, then the combination acts as a:
1. NAND gate
2. NOR gate
3. AND gate
4. OR gate
1. NAND gate
2. NOR gate
3. AND gate
4. OR gate
Subtopic: Logic gates |
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Level 1: 80%+
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The \(I\text-V\) characteristics shown below are exhibited by a:
| 1. | Light-emitting diode | 2. | Zener diode |
| 3. | Photodiode | 4. | Solar cell |
Subtopic: Applications of PN junction |
65%
Level 2: 60%+
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